circuit MYAccumulators :
  module MYAccumulator :
    input clock : Clock
    input reset : Reset
    output io : { accumIn : { flip waddr : UInt<4>, flip wen : UInt<1>, flip wclear : UInt<1>, flip lastvec : UInt<1>}, flip raddr : UInt<4>, flip dataIn : SInt<32>, flip accumOut : { flip waddr : UInt<4>, flip wen : UInt<1>, flip wclear : UInt<1>, flip lastvec : UInt<1>}, dataOut : SInt<32>}

    smem mem : SInt<32> [16] @[Accumulator.scala 38:30]
    when io.accumIn.wen : @[Accumulator.scala 40:29]
      when io.accumIn.wclear : @[Accumulator.scala 41:40]
        write mport MPORT = mem[io.accumIn.waddr], clock
        MPORT <= io.dataIn
      else :
        wire _WIRE : UInt @[Accumulator.scala 44:73]
        _WIRE is invalid @[Accumulator.scala 44:73]
        when UInt<1>("h1") : @[Accumulator.scala 44:73]
          _WIRE <= io.accumIn.waddr @[Accumulator.scala 44:73]
          node _T = or(_WIRE, UInt<4>("h0")) @[Accumulator.scala 44:73]
          node _T_1 = bits(_T, 3, 0) @[Accumulator.scala 44:73]
          read mport MPORT_1 = mem[_T_1], clock @[Accumulator.scala 44:73]
        node _T_2 = add(io.dataIn, MPORT_1) @[Accumulator.scala 44:63]
        node _T_3 = tail(_T_2, 1) @[Accumulator.scala 44:63]
        node _T_4 = asSInt(_T_3) @[Accumulator.scala 44:63]
        write mport MPORT_2 = mem[io.accumIn.waddr], clock
        MPORT_2 <= _T_4
    wire _io_dataOut_WIRE : UInt @[Accumulator.scala 48:31]
    _io_dataOut_WIRE is invalid @[Accumulator.scala 48:31]
    when UInt<1>("h1") : @[Accumulator.scala 48:31]
      _io_dataOut_WIRE <= io.raddr @[Accumulator.scala 48:31]
      node _io_dataOut_T = or(_io_dataOut_WIRE, UInt<4>("h0")) @[Accumulator.scala 48:31]
      node _io_dataOut_T_1 = bits(_io_dataOut_T, 3, 0) @[Accumulator.scala 48:31]
      read mport io_dataOut_MPORT = mem[_io_dataOut_T_1], clock @[Accumulator.scala 48:31]
    io.dataOut <= io_dataOut_MPORT @[Accumulator.scala 48:20]
    reg io_accumOut_waddr_REG : UInt, clock with :
      reset => (reset, UInt<1>("h0")) @[Accumulator.scala 50:37]
    io_accumOut_waddr_REG <= io.accumIn.waddr @[Accumulator.scala 50:37]
    io.accumOut.waddr <= io_accumOut_waddr_REG @[Accumulator.scala 50:27]
    reg io_accumOut_wen_REG : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[Accumulator.scala 51:37]
    io_accumOut_wen_REG <= io.accumIn.wen @[Accumulator.scala 51:37]
    io.accumOut.wen <= io_accumOut_wen_REG @[Accumulator.scala 51:27]
    reg io_accumOut_wclear_REG : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[Accumulator.scala 52:37]
    io_accumOut_wclear_REG <= io.accumIn.wclear @[Accumulator.scala 52:37]
    io.accumOut.wclear <= io_accumOut_wclear_REG @[Accumulator.scala 52:27]
    reg io_accumOut_lastvec_REG : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[Accumulator.scala 53:38]
    io_accumOut_lastvec_REG <= io.accumIn.lastvec @[Accumulator.scala 53:38]
    io.accumOut.lastvec <= io_accumOut_lastvec_REG @[Accumulator.scala 53:28]

  module MYAccumulator_1 :
    input clock : Clock
    input reset : Reset
    output io : { accumIn : { flip waddr : UInt<4>, flip wen : UInt<1>, flip wclear : UInt<1>, flip lastvec : UInt<1>}, flip raddr : UInt<4>, flip dataIn : SInt<32>, flip accumOut : { flip waddr : UInt<4>, flip wen : UInt<1>, flip wclear : UInt<1>, flip lastvec : UInt<1>}, dataOut : SInt<32>}

    smem mem : SInt<32> [16] @[Accumulator.scala 38:30]
    when io.accumIn.wen : @[Accumulator.scala 40:29]
      when io.accumIn.wclear : @[Accumulator.scala 41:40]
        write mport MPORT = mem[io.accumIn.waddr], clock
        MPORT <= io.dataIn
      else :
        wire _WIRE : UInt @[Accumulator.scala 44:73]
        _WIRE is invalid @[Accumulator.scala 44:73]
        when UInt<1>("h1") : @[Accumulator.scala 44:73]
          _WIRE <= io.accumIn.waddr @[Accumulator.scala 44:73]
          node _T = or(_WIRE, UInt<4>("h0")) @[Accumulator.scala 44:73]
          node _T_1 = bits(_T, 3, 0) @[Accumulator.scala 44:73]
          read mport MPORT_1 = mem[_T_1], clock @[Accumulator.scala 44:73]
        node _T_2 = add(io.dataIn, MPORT_1) @[Accumulator.scala 44:63]
        node _T_3 = tail(_T_2, 1) @[Accumulator.scala 44:63]
        node _T_4 = asSInt(_T_3) @[Accumulator.scala 44:63]
        write mport MPORT_2 = mem[io.accumIn.waddr], clock
        MPORT_2 <= _T_4
    wire _io_dataOut_WIRE : UInt @[Accumulator.scala 48:31]
    _io_dataOut_WIRE is invalid @[Accumulator.scala 48:31]
    when UInt<1>("h1") : @[Accumulator.scala 48:31]
      _io_dataOut_WIRE <= io.raddr @[Accumulator.scala 48:31]
      node _io_dataOut_T = or(_io_dataOut_WIRE, UInt<4>("h0")) @[Accumulator.scala 48:31]
      node _io_dataOut_T_1 = bits(_io_dataOut_T, 3, 0) @[Accumulator.scala 48:31]
      read mport io_dataOut_MPORT = mem[_io_dataOut_T_1], clock @[Accumulator.scala 48:31]
    io.dataOut <= io_dataOut_MPORT @[Accumulator.scala 48:20]
    reg io_accumOut_waddr_REG : UInt, clock with :
      reset => (reset, UInt<1>("h0")) @[Accumulator.scala 50:37]
    io_accumOut_waddr_REG <= io.accumIn.waddr @[Accumulator.scala 50:37]
    io.accumOut.waddr <= io_accumOut_waddr_REG @[Accumulator.scala 50:27]
    reg io_accumOut_wen_REG : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[Accumulator.scala 51:37]
    io_accumOut_wen_REG <= io.accumIn.wen @[Accumulator.scala 51:37]
    io.accumOut.wen <= io_accumOut_wen_REG @[Accumulator.scala 51:27]
    reg io_accumOut_wclear_REG : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[Accumulator.scala 52:37]
    io_accumOut_wclear_REG <= io.accumIn.wclear @[Accumulator.scala 52:37]
    io.accumOut.wclear <= io_accumOut_wclear_REG @[Accumulator.scala 52:27]
    reg io_accumOut_lastvec_REG : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[Accumulator.scala 53:38]
    io_accumOut_lastvec_REG <= io.accumIn.lastvec @[Accumulator.scala 53:38]
    io.accumOut.lastvec <= io_accumOut_lastvec_REG @[Accumulator.scala 53:28]

  module MYAccumulator_2 :
    input clock : Clock
    input reset : Reset
    output io : { accumIn : { flip waddr : UInt<4>, flip wen : UInt<1>, flip wclear : UInt<1>, flip lastvec : UInt<1>}, flip raddr : UInt<4>, flip dataIn : SInt<32>, flip accumOut : { flip waddr : UInt<4>, flip wen : UInt<1>, flip wclear : UInt<1>, flip lastvec : UInt<1>}, dataOut : SInt<32>}

    smem mem : SInt<32> [16] @[Accumulator.scala 38:30]
    when io.accumIn.wen : @[Accumulator.scala 40:29]
      when io.accumIn.wclear : @[Accumulator.scala 41:40]
        write mport MPORT = mem[io.accumIn.waddr], clock
        MPORT <= io.dataIn
      else :
        wire _WIRE : UInt @[Accumulator.scala 44:73]
        _WIRE is invalid @[Accumulator.scala 44:73]
        when UInt<1>("h1") : @[Accumulator.scala 44:73]
          _WIRE <= io.accumIn.waddr @[Accumulator.scala 44:73]
          node _T = or(_WIRE, UInt<4>("h0")) @[Accumulator.scala 44:73]
          node _T_1 = bits(_T, 3, 0) @[Accumulator.scala 44:73]
          read mport MPORT_1 = mem[_T_1], clock @[Accumulator.scala 44:73]
        node _T_2 = add(io.dataIn, MPORT_1) @[Accumulator.scala 44:63]
        node _T_3 = tail(_T_2, 1) @[Accumulator.scala 44:63]
        node _T_4 = asSInt(_T_3) @[Accumulator.scala 44:63]
        write mport MPORT_2 = mem[io.accumIn.waddr], clock
        MPORT_2 <= _T_4
    wire _io_dataOut_WIRE : UInt @[Accumulator.scala 48:31]
    _io_dataOut_WIRE is invalid @[Accumulator.scala 48:31]
    when UInt<1>("h1") : @[Accumulator.scala 48:31]
      _io_dataOut_WIRE <= io.raddr @[Accumulator.scala 48:31]
      node _io_dataOut_T = or(_io_dataOut_WIRE, UInt<4>("h0")) @[Accumulator.scala 48:31]
      node _io_dataOut_T_1 = bits(_io_dataOut_T, 3, 0) @[Accumulator.scala 48:31]
      read mport io_dataOut_MPORT = mem[_io_dataOut_T_1], clock @[Accumulator.scala 48:31]
    io.dataOut <= io_dataOut_MPORT @[Accumulator.scala 48:20]
    reg io_accumOut_waddr_REG : UInt, clock with :
      reset => (reset, UInt<1>("h0")) @[Accumulator.scala 50:37]
    io_accumOut_waddr_REG <= io.accumIn.waddr @[Accumulator.scala 50:37]
    io.accumOut.waddr <= io_accumOut_waddr_REG @[Accumulator.scala 50:27]
    reg io_accumOut_wen_REG : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[Accumulator.scala 51:37]
    io_accumOut_wen_REG <= io.accumIn.wen @[Accumulator.scala 51:37]
    io.accumOut.wen <= io_accumOut_wen_REG @[Accumulator.scala 51:27]
    reg io_accumOut_wclear_REG : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[Accumulator.scala 52:37]
    io_accumOut_wclear_REG <= io.accumIn.wclear @[Accumulator.scala 52:37]
    io.accumOut.wclear <= io_accumOut_wclear_REG @[Accumulator.scala 52:27]
    reg io_accumOut_lastvec_REG : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[Accumulator.scala 53:38]
    io_accumOut_lastvec_REG <= io.accumIn.lastvec @[Accumulator.scala 53:38]
    io.accumOut.lastvec <= io_accumOut_lastvec_REG @[Accumulator.scala 53:28]

  module MYAccumulators :
    input clock : Clock
    input reset : UInt<1>
    output io : { accumsIn : { flip waddr : UInt<4>, flip wen : UInt<1>, flip wclear : UInt<1>, flip lastvec : UInt<1>}, flip datasIn : SInt<32>[3], flip raddr : UInt<4>, datasOut : SInt<32>[3], done : UInt<1>}

    inst MYAccumulator of MYAccumulator @[Accumulator.scala 69:23]
    MYAccumulator.clock <= clock
    MYAccumulator.reset <= reset
    inst MYAccumulator_1 of MYAccumulator_1 @[Accumulator.scala 69:23]
    MYAccumulator_1.clock <= clock
    MYAccumulator_1.reset <= reset
    inst MYAccumulator_2 of MYAccumulator_2 @[Accumulator.scala 69:23]
    MYAccumulator_2.clock <= clock
    MYAccumulator_2.reset <= reset
    MYAccumulator.io.accumIn.lastvec <= io.accumsIn.lastvec @[Accumulator.scala 76:46]
    MYAccumulator.io.accumIn.wclear <= io.accumsIn.wclear @[Accumulator.scala 76:46]
    MYAccumulator.io.accumIn.wen <= io.accumsIn.wen @[Accumulator.scala 76:46]
    MYAccumulator.io.accumIn.waddr <= io.accumsIn.waddr @[Accumulator.scala 76:46]
    MYAccumulator.io.raddr <= io.raddr @[Accumulator.scala 77:46]
    MYAccumulator.io.dataIn <= io.datasIn[0] @[Accumulator.scala 78:46]
    MYAccumulator_1.io.accumIn.lastvec <= MYAccumulator.io.accumOut.lastvec @[Accumulator.scala 80:46]
    MYAccumulator_1.io.accumIn.wclear <= MYAccumulator.io.accumOut.wclear @[Accumulator.scala 80:46]
    MYAccumulator_1.io.accumIn.wen <= MYAccumulator.io.accumOut.wen @[Accumulator.scala 80:46]
    MYAccumulator_1.io.accumIn.waddr <= MYAccumulator.io.accumOut.waddr @[Accumulator.scala 80:46]
    MYAccumulator_1.io.raddr <= io.raddr @[Accumulator.scala 81:44]
    MYAccumulator_1.io.dataIn <= io.datasIn[1] @[Accumulator.scala 82:47]
    MYAccumulator_2.io.accumIn.lastvec <= MYAccumulator_1.io.accumOut.lastvec @[Accumulator.scala 80:46]
    MYAccumulator_2.io.accumIn.wclear <= MYAccumulator_1.io.accumOut.wclear @[Accumulator.scala 80:46]
    MYAccumulator_2.io.accumIn.wen <= MYAccumulator_1.io.accumOut.wen @[Accumulator.scala 80:46]
    MYAccumulator_2.io.accumIn.waddr <= MYAccumulator_1.io.accumOut.waddr @[Accumulator.scala 80:46]
    MYAccumulator_2.io.raddr <= io.raddr @[Accumulator.scala 81:44]
    MYAccumulator_2.io.dataIn <= io.datasIn[2] @[Accumulator.scala 82:47]
    io.datasOut[0] <= MYAccumulator.io.dataOut @[Accumulator.scala 87:32]
    io.datasOut[1] <= MYAccumulator_1.io.dataOut @[Accumulator.scala 87:32]
    io.datasOut[2] <= MYAccumulator_2.io.dataOut @[Accumulator.scala 87:32]
    io.done <= MYAccumulator_2.io.accumOut.lastvec @[Accumulator.scala 90:17]

